1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of integrating scatterometry metrology directly into die design, and a substrate having one or more die that are substantially comprised of grating structures used in scatterometry measurement techniques.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modem semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modem devices. For example, gate electrodes may now be patterned to a width 12 that is approximately 0.2 xcexcm (2000 xc3x85), and further reductions are planned in the future. As stated previously, the width 12 of the gate electrode 14 corresponds approximately to the channel length 13 of the transistor 10 when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance.
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting substrate. FIG. 2 depicts an illustrative embodiment of a semiconducting substrate or wafer 11 that may be found in modem semiconductor manufacturing operations. As shown in FIG. 2, a plurality of production die 42 are formed above the wafer 11. The production die 42 define the area of the wafer 11 where production integrated circuit devices, e.g., microprocessors, ASICs, memory devices, etc., will be formed. The size, shape and number of production die 42 per wafer 11 depend upon the type of device under construction. For example, several hundred production die 42 may be formed above an 8-inch diameter wafer 11. The wafer 11 may also have an alignment notch 17 that is used to provide relatively rough alignment of the wafer 11 prior to performing certain processes, e.g., an exposure process in a stepper tool. The space between the production die 42 is generally referred to as scribe lines 41. After the integrated circuits are completely formed on the production die 42, the wafer 11 will be cut along the scribe lines 41 and packaged and sold. Typically, the production die 42 are packed very close together, i.e., the scribe lines 41 may have a width that ranges from approximately 25-200 xcexcm.
During the course of manufacturing integrated circuit devices, it is highly desirable and important to obtain as much information as possible regarding how well the processes used to form the various features, e.g., gate electrodes, metal lines, trenches, etc., performed. To this end, a variety of metrology tests and tools are used to obtain a variety of data regarding the processes and resulting features formed on an integrated circuit device. For example, an ellipsometer may be used to determine the thickness of a previously formed layer of material, e.g., silicon dioxide. Similarly, a scanning electron microscope may be used to approximately determine the critical dimension of gate electrode structures 14 after they have been formed.
Scatterometry is another metrology technique that has found application within semiconductor manufacturing operations. Typically, scatterometry involves the formation of one or more grating structures 25 that will be subsequently measured using a scatterometry tool. These grating structures 25 may be positioned at various locations on the wafer 11, and they may be oriented in multiple directions. Typically, the grating structures 25 are located in the scribe lines 41 of the wafers 11. Seven illustrative grating structures 25 are depicted in FIG. 2. The size and shape of the grating structures 25 may be varied, but they do tend to be relatively large, e.g., they may be formed in an area having dimensions of approximately 100xc3x97120 xcexcm. Given the size of these grating structures 25, there may be some situations where, given current practices, one or more of the grating structures 25 cannot be placed in an ideal location. In turn, this may deny the process engineer valuable metrology data that may be useful in improving manufacturing operations.
Given the scarcity of available plot space, the positioning of the grating structures 25 across the surface of the substrate 11 is often dictated by what plot space is left after the formation of the production die 42. That is, simply put, the placement of the grating structures 25 is given a very low priority compared to the placement of production die 42. This can be problematic in that, all other things being equal, it would be desirable to locate the grating structures 25 used in scatterometric metrology techniques at locations where the most benefit may be derived. For example, all other things being equal, it would be desirable to locate the grating structures 25 at positions on the wafer such that the scatterometry tools may more accurately reflect the processing to which the production integrated circuit devices are subjected. By way of example, it may be desirable to examine the effectiveness of a process used to form gate electrode structures in relation to how densely packed the structures are relative to other surrounding structures. That is, a process used to form an isolated gate electrode structure may produce different results, i.e., critical dimensions, as compared to using the same process in which a plurality of gate electrode structures are formed in a very densely-packed environment. In such situations, it may be desirable to locate a grating structure 25 in a densely-packed environment, but such environments are not available in the scribe lines 41 of the wafer 11.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is directed to a method of integrating scatterometry metrology structures directly into die design. In one embodiment, the present invention is directed to a wafer comprised of a semiconducting substrate, a plurality of production die formed on the substrate, and at least one non-production die formed on the substrate, the non-production die having at least one grating structure formed therein that will be measured in subsequent metrology tests. The number of such non-production die, as well as the number of grating structures in each non-production die, may vary. Moreover, the size, shape and configuration of the grating structures may vary from die to die, and within a die.
In another illustrative embodiment, the present invention is also directed to a method comprised of providing a semiconducting substrate, forming at least one production integrated circuit device in a plurality of production die formed on the substrate, and forming at least one grating structure in at least one non-production die formed on the substrate. The method further comprises illuminating said grating structure formed in the non-production die and measuring light reflected off of the illuminated grating structure to generate an optical characteristic trace for the illuminated grating structure formed in the non-production die.